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Ph.D. Thesis
High-Level Verification of System Designs. PDF
Journal Papers
Sudipta Kundu and Sorin Lerner. Translation Validation in
High-Level Synthesis. In Submission, 2009.
Sudipta Kundu,
Sorin Lerner and Rajesh Gupta. High-Level Verification. In IPSJ
Transactions on System LSI Design Methodology, 2009.
(Invited Paper).
Conference Papers
Chao Wang, Sudipta Kundu, Malay Ganai, and
Aarti Gupta. Symbolic Predictive Analysis for
Concurrent Programs. In FM ’09: Proceedings of the 16th International
Symposium on Formal Methods, 2009.
Malay Ganai and Sudipta Kundu. Reduction of
Verification Conditions for Concurrent System using Mutually Atomic
Transactions. In SPIN ’09: Proceedings of the 16th
International SPIN Workshop on Model Checking of Software, 2009.
Sudipta Kundu,
Zachary Tatlock, and Sorin Lerner. Proving Optimizations
Correct using Parameterized Program Equivalence. In PLDI
’09: Proceedings of the 2009 ACM
SIGPLAN conference on Programming Language Design and Implementation,
2009.
Sudipta Kundu, Sorin Lerner,
and Rajesh Gupta. Validating High-Level Synthesis. International Conference on Computer Aided
Verification (CAV'08),
Princeton, NJ, USA,
2008. Published
Paper Presentation
Sudipta Kundu, Malay Ganai, and
Rajesh Gupta. Partial Order Reduction for Scalable Testing of SystemC
TLM Designs. Design Automation
Conference (DAC'08),
Anaheim, CA, USA, 2008. Published
Paper Presentation
Sudipta Kundu, Sorin Lerner,
and Rajesh Gupta. Automated Refinement Checking of Concurrent Systems.
In ICCAD ’07: Proceedings
of the 2007 IEEE/ACM international
conference on Computer-aided design, pages 318–325, Piscataway, NJ,
USA, 2007. IEEE Press. Technical Report Published Paper Presentation
Gurashis Singh Brar, Sudipta Kundu,
Pratik Worah, Susmit Biswas, Arijit Mukherjee, and Anupam Basu.OaSis:
An Application Specific Operating System for an Embedded Environment.
In VLSI Design ’04: 17th
International Conference on VLSI Design,
with the 3rd International Conference on Embedded Systems Design,
pages 776–779, Mumbai, India, 2004. IEEE Press. Full Paper Published Paper
In Preparation
Frederic Doucet, Sudipta
Kundu, Ingolf H. Kruger, R.K. Shyamasundar and Rajesh Gupta.
Compositional Design Methodology for Scalable Verification of System
Design. In Preparation, 2009.
Patents
Malay Ganai and Sudipta
Kundu. Partial Order Reduction for Scalable Testing in System
Level Design. US Patent Pending, 2008.
Malay Ganai and Sudipta
Kundu. Reduction of Verification Conditions for a
Concurrent System using MATs. US Patent Pending, 2008.
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