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• Takes plain ANSI-C Input (see restrictions below) and produces synthesizable register-transfer level (RTL) VHDL. VHDL is fully synthesizable by Synopsys Design Compiler; support for Xilinx XST will be available by next release (in a few weeks).
• Takes a resource library and synthesis scripts as additional input. A recommended synthesis script and a sample resource library is shipped with the distribution.
• Applies pre-synthesis (source-to-source) transformations such as loop unrolling, loop-invariant code motion, common sub-expression elimination (CSE), dead code elimination, copy and constant propagation.
• Does high-level synthesis scheduling and applies a range of compiler and synthesis transformations: speculative code motions, dynamic transformations (dynamic CSE and dynamic branch balancing),
• Supports operation chaining.
• Enables designer-controlled loop unrolling and loop pipelining (loop shifting) through scripts.
• The parallelizing transformations used by SPARK during synthesis lead to quality of synthesis results (in terms of circuit delay and area after logic synthesis) that are higher than those achievable by standard high-level synthesis flows.
• Script and command-line option based control over the passes, transformations, and heuristics used by SPARK enables design space exploration and also, research into new heuristics.

SPARK does not currently support pipelining.

SPARK supports pure ANSI-C with no additions or special constructs. SPARK extracts parallelism from this C description. Here are the restrictions on the input "C" (see User Manual for details and workarounds for some of these):

• No support for pointers. However, arrays and array accesses of the type arr[index variable expression] are supported. Also, passing arguments by reference to a function is also supported.
• No support for function recursion.
• No support for irregular jumps through $goto$. Some of these can be resolved in a state machine, but they adversely affect our ability to apply transformations.

• No support for multi-dimension arrays. Multi-dimensional arrays can be reduced manually to single-dimensional arrays. For example: consider an array a[N][M]. This can be re-declared as a[N*M]. Any access to a[i][j] then becomes a[i*M+j].
• Limited support for structs and unions.  Also, no VHDL generation for user-defined data types.
• Poor support for expressions of type (a ? b : c). We advise changing this expression to the following statement:
  if(a)   b
  else   c