References

[1]

S. Gupta. Coordinated Coarse-Grain and Fine-Grain Optimizations for High-Level Synthesis. PhD thesis, University of California, Irvine, 2003.

[2]

S. Gupta, N.D. Dutt, R.K. Gupta, and A. Nicolau. SPARK: A high-level synthesis framework for applying parallelizing compiler transformations. In International Conference on VLSI Design, 2003.

[3]

SPARK parallelizing high-level synthesis framework website. http://www.cecs.uci.edu/~spark.

[4]

S. Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta, and A. Nicolau. Speculation techniques for high level synthesis of control intensive designs. In Design Automation Conference, 2001.

[5]

S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta, and A. Nicolau. Conditional speculation and its effects on performance and area for high-level synthesis. In International Symposium on System Synthesis, 2001.

[6]

S. Gupta, M. Reshadi, N. Savoiu, N.D. Dutt, R.K. Gupta, and A. Nicolau. Dynamic common sub-expression elimination during scheduling in high-level synthesis. In International Symposium on System Synthesis, 2002.

[7]

S. Gupta, N.D. Dutt, R.K. Gupta, and A. Nicolau. Dynamic conditional branch balancing during the high-level synthesis of control-intensive designs. In Design, Automation and Test Conference, 2003.

[8]

S. Gupta, N.D. Dutt, R.K. Gupta, and A. Nicolau. Dynamically increasing the scope of code motions during the high-level synthesis of digital circuits. Invited Paper in Special Issue of IEE Proceedings: Computers and Digital Technique: Best of DATE 2003, 150(5), September 2003.

[9]

S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta, and A. Nicolau. Using global code motions to improve the quality of results for high-level synthesis. Technical Report CECS-TR-02-29, Center for Embedded Computer Systems, Univ. of California, Irvine, 2002.

[10]

A. Aho, R. Sethi, and J. Ullman. Compilers: Principles and Techniques and Tools. Addison-Wesley, 1986.

[11]

Z. Navabi. VHDL: Analysis and Modeling of Digital Systems. McGraw-Hill, 1993.

[12]

M. Molina, J. Mendias, and R. Hermida. High-level allocation to minimize internal hardware wastage. In Design, Automation and Test in Europe, 2003.

[13]

A. Nicolau and S. Novack. Trailblazing: A hierarchical approach to Percolation Scheduling. In International Conference on Parallel Processing, 1993.

[14]

M. Girkar and C.D. Polychronopoulos. Automatic extraction of functional parallelism from ordinary programs. IEEE Trans. on Parallel & Distributed Systems, Mar. 1992.

[15]

Edison Design Group (edg) compiler frontends. http://www.edg.com.

[16]

S. Gupta, T. Kam, M. Kishinevsky, S. Rotem, N. Savoiu, N.D. Dutt, R.K. Gupta, and A. Nicolau. Coordinated transformations for high-level synthesis of high performance microprocessor blocks. In Design Automation Conference, 2002.

[17]

AT&T Research Labs. Graphviz - Open source graph drawing software. http://www.research.att.com/sw/tools/graphviz/.