Spark writes out several files such as the output graphs (see next section) and the backend VHDL and C files. All these files are written out to the subdirectory ``output'' of the directory from which Spark is invoked. This directory has to be created before executing Spark.
Flag Purpose -h Prints help -hs Schedule Design -hvf Generate RTL VHDL (output file is ./output/filename_spark_rtl.vhd) -hb Do all Resource Binding (operation to functional unit and variable to registers) -hec Some statistics about states, path lengths are printed into the backend VHDL file -hcc Generate output C file of scheduled design (output file is ./output/filename_sparkout.c) -hch Chain operations across Conditional Boundaries -hcp Do Copy and Constant Propagation -hdc Do Dead Code Elimination -hcs Do Common Sub-Expression Elimination -hli Do Loop Invariant Code Motion -hg Generate graphs (output files are in directory ./output). Graphs are generated by default if scheduling is done, as: filename_sched.dotty -hcg Generate function call graph (./output/CG_filename.dotty) -hq Run quietly; no debug messages
For example, use the ``-m'' command-line flag for input code in which functions are specified in the following format:
Flag Purpose -m For old style C (see below) -c99 For C conforming to the C99 specification
void myfunction(variableA, variableB)
int variableA;
int variableB;
{
..
}
|
Graphs representing the original input file Graphs representing the scheduled design CFG_filename_c_functionName.dotty CFG_filename_c_functionName_sched.dotty HTG_filename_c_functionName.dotty HTG_filename_c_functionName_sched.dotty DFG_filename_c_functionName.dotty DFG_filename_c_functionName_sched.dotty CDFG_filename_c_functionName.dotty CDFG_filename_c_functionName_sched.dotty CG_filename_c_functionName.dotty - CG_DFG_filename_c_functionName.dotty -
Table 4.1: Output Dotty graphs generated by Spark
To view these output graphs, we use the Graphviz command line tool dotty, as follows:
Abbreviation Explanation CFG Control Flow Graph: Basic blocks with control flow between them HTG Hierarchical Task Graph: Hierarchical structure of basic blocks DFG Data Flow Graph: data flow between operations CDFG Control-Data Flow Graph: Resource-utilization based view of the CFG CG Call Graph showing control flow between functions CG_DFG Call Graph with data dependencies and control flow between functions filename The name of ``C'' input file functionName The name of the function in input file
Table 4.2: Key to abbreviations used in Dotty graph naming
// ClockPeriod NumOfCycles TimeConstrained Pipelined
[GeneralInfo]
10 0 0 0
|
//typeName lowerRange upperRange
//or variableName lowerRange upperRange
[TypeInfo]
int -32767 32768
myVar 0 16
|
//name type inpsType inputs outputs number cost cycles ns [Resources] CMP ==,<,!= i 2 1 1 10 1 10 |
//name type inpsType inputs outputs number cost cycles ns [Resources] ALU +,- i 2 1 1 10 1 10 ADD + i 2 1 1 10 1 10 |
Resource Operator Operation Number of Type in C Inputs + + add 2 - - subtract 2 * * multiply 2 / / divide 2 != != compare 2 == == compare 2 > > compare 2 < < compare 2 >= >= compare 2 <= <= compare 2 << << shift 2 >> >> shift 2 [] [] array access 1 ~ ~ complement 1 ! ! logical not 1 && && logical and 2 || || logical or 2 b& & Boolean and 2 b| | Boolean or 2 call - function call -
Figure 4.1: List of all resource types, corresponding C operators, operation name, and number of inputs
//name type inpsType inputs outputs number cost cycles ns [Resources] myfunction call i 0 0 2 10 1 10 |
//name type inpsType inputs outputs number cost cycles ns [Resources] ALLCALLS call i 0 0 1 10 1 10 |
// variable maxNumUnrolls maxNumShifts percentageThreshold ThruputCycles [RDLPParams] * 0 0 70 0 i 0 2 70 0 |
Note that, from release version 1.1 on, the output VHDL file generated by Spark has the extension ``.vhd'' versus the earlier ``.vhdl''. This is for compatibility with Windows based tools such as Xilinx XST that look for .vhd VHDL files by default.
if CURRENT_STATE(0) = '1' then regNum0 <= res_ALU_1_out; regNum5 <= 0; elsif CURRENT_STATE(1) = '1' then regNum1 <= res_ALU_0_out; regNum2 <= res_ALU_1_out; hT0 <= res_CMP_2_out;
if CURRENT_STATE(0) = '1' then hT5 <= (x + 2); col <= 0; elsif CURRENT_STATE(1) = '1' then hT14 <= (col + bytes); hT15 <= (col - x); hT0 <= (col < 10);
(a) (b)
Figure 4.2: (a) Bound VHDL code (b) Corresponding unbound VHDL code
[OutputVHDLRules] PrintSynopsysVHDL=true |
[OutputVHDLRules] PrintSynopsysVHDL=false |
18cm
//line format: functiontype=functionvalue [SchedulerFunctions] CandidateValidatorFunction=candidateValidatorPriority // Candidate Validation Algorithm CandidateMoverFunction=TbzMover // Use Trailblazing for code motions CandidateRegionWalkerFunction=topDownGlobal // Design traversal for candidate operations ScheduleRegionWalkerFunction=topDownBasicBlock // Design traversal for scheduling PreSchedulingFunction=initPriorities // Calculate priorities of operations before scheduling PriorityType=max // Calculate priority as max or sum of dependent operations data dependencies PostSchedulingStepFunction=postSchedulingPriority // Reverse speculate all unscheduled operations at each time step of scheduling PreSchedulingStepFunction=preSchedPriority // Do early condition execution before each time step of scheduling LoopSchedulingFunction=RDLP // Loop unrolling is done by RDLP PreLoopSchedulingFunction=prepareForRDLP // Initialization functions for loops PostLoopSchedulingFunction=constantPropagation // Optional post loop scheduling pass ReDoHTGsForDupUp=false // Whether to reschedule HTGs for possible duplication-up true or false ReassignPriorityForCS=true // Reassign priorities to favor operations within basic blocks RestrictDupUpType=targetBBUnsched // Restrict duplication-up DynamicCSE=true // Whether Dynamic CSE is enabled or not BranchBalancingDuringCMs=true // Enable branch balancing during code motions BranchBalancingDuringTraversal=true // Enable branch balancing during design traversal
Figure 4.3: The scheduler functions section in a sample Priority.rules file.
// all the following can take values true or false [CodeMotionRules] RenamingAllowed=true // Variable Renaming allowed or not AcrossHTGCodeMotionAllowed=true // Across HTG code motion allowed or not SpeculationAllowed=true // Speculation allowed allowed or not ReverseSpeculationAllowed=true // Reverse Speculation allowed or not EarlyCondExecAllowed=true // Early Condition Execution allowed or not ConditionalSpeculationAllowed=true // Condition Speculation allowed or not |
[CodeMotionCosts] WithinBB 1 AcrossHTGCodeMotion 1 Speculation 1 DuplicationUp 1 |