SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits


SPARK is a C-to-VHDL high-level synthesis framework that employs a set of innovative compiler, parallelizing compiler, and synthesis transformations to improve the quality of high-level synthesis results. The compiler transformations have been re-instrumented for synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware cost models. The SPARK parallelizing high-level synthesis methodology is particularly targeted to multimedia and image processing applications along with control-intensive microprocessor functional blocks. We validated the effectiveness of our approach and evaluated the various optimizations for large real-life applications such as the Instruction Length Decoder from the Intel Pentium and multimedia applications such as MPEG-1, MPEG-2 and the GIMP image processing tool.

SPARK takes behavioral ANSI-C code as input, schedules it using speculative code motions and loop transformations, runs an interconnect-minimizing resource binding pass and generates a finite state machine for the scheduled design graph. Finally, a backend code generation pass outputs synthesizable register-transfer level (RTL) VHDL. This VHDL can then by synthesized using logic synthesis tools into an ASIC or by mapped onto a FPGA.

SPARK is a project of the Microelectronic Embedded Systems Laboratory.

Project Researchers

Sumit Gupta (Graduated June 2003)
Nick Savoiu

Sudipta Kundu


Prof. Rajesh Gupta (Primary Investigator)
Prof. Nikil Dutt
Prof. Alex Nicolau

Other Graduate Students who contributed to SPARK

Mehrdad Reshadi
Sunwoo Kim

Industry Liasons

Conexant: Chuck Siska
Intel: Shai Rotem, Mike Kishinevski and Timothy Kam
Motorola: Paul Kritzinger

The SPARK project is funded by the
Semiconductor Research Corporation and Intel Strategic CAD Labs

If you came here looking for the SPARK Ada software development product, please try the SPARK Ada website

Maintained by Sumit Gupta <sumitg at>