Our research projects at MESL span the entire range
of embedded systems and software, from hardware level synthesis
to theory and algorithms for wireless sensor networks.
CERTUS: COMPOSITIONAL MODELING, REGULARIZING SYNTHESIS AND OPTIMIZATION FOR ACCELERATOR-CENTRIC ASIC
The focus of CERTUS project is on high-performance systems-on-chips that contain one or more processing elements, usually in the form of an IP block produced from commercial vendors and supported by publicly-available software development tools. There are three main technical barriers that CERTUS seeks to overcome: (a) compositional methods that allow systematic reuse of designed blocks including verification results; (b) scaling and porting of high-performance analog circuit blocks; (c) formal capture and reasoning of design data flow across multiple tool chains to enable process portability.
As semiconductor manufacturers build ever smaller components, circuits and chips at the nano scale become less reliable and more expensive to produce - no longer behaving like precisely chiseled machines with tight tolerances. Modern computing tends to ignore the variability in behavior of underlying system components from device to device, their wear-out over time, or the environment in which the computing system is placed. This makes them expensive, fragile and vulnerable to even the smallest changes in the environment or component failures. The Variability Expedition envisions a computing world where system components -- led by proactive software -- routinely monitor, predict and adapt to the variability of manufactured systems. Changing the way software interacts with hardware offers the best hope for perpetuating the fundamental gains in computing performance at lower cost of the past 40 years.
The Variability Expedition fundamentally rethinks the rigid, deterministic hardware-software interface, to propose a new class of computing machines that are not only adaptive but also highly energy efficient. These machines will be able to discover the nature and extent of variations in hardware, develop abstractions to capture these variations, and drive adaptations in the software stack from compilers, runtime to applications. The resulting computer systems will work and continue working while using components that vary in performance or grow less reliable over time and across technology generations. A fluid software-hardware interface will thus mitigate the variability of manufactured systems and make machines robust, reliable and responsive to changing operating conditions.
RoseLine: Enabling Robust, Secure and Efficient Knowledge of Time Across the System Stack is a collaborative project funded by the National Science Foundation under its Cyber-Physical Systems program, and involves researchers from CMU, UCLA, UCSB, UCSD, and the University of Utah.
Accurate and reliable knowledge of time is fundamental to cyber-physical systems for sensing, control, performance, and energy efficient integration of computing and communications. This simple statement underlies the RoseLine project. Emerging CPS applications depend on precise knowledge of time to infer location and control communication. There is a diversity of semantics used to describe time, and quality of time varies as we move up and down the system stack. System designs tend to overcompensate for these uncertainties and the result is systems that may be over designed, in-efficient, and fragile. The intellectual merit derives from the new and fundamental concept of time and the holistic measure of quality of time (QoT) that captures metrics including resolution, accuracy, and stability.
The project will build a system stack that enables new ways for clock hardware, OS, network services, and applications to learn, maintain and exchange information about time, influence component behavior, and robustly adapt to dynamic QoT requirements, as well as to benign and adversarial changes in operating conditions. Application areas that will benefit from Quality of Time will include: smart grad, networked and coordinated control of aerospace systems, underwater sensing, and industrial automation. The broader impact of the proposal is due to the foundational nature of the work which builds a robust and tunable quality of time that can be applied across a broad spectrum of applications that pervade modern life.
Our research focuses on energy efficiency aspects of systems from load balancing in data centers to EV integration in smart grid. The main tool for achieving energy efficiency in most of our work is the flexibility in time that comes from the service level agreements (SLAs) between service provider and service receiver. As these systems are often online i.e. future information is not available at the time of execution, we name our approach as 'dynamic deferral'. We have devised spatiotemporal dynamic deferral techniques for load balancing in geographically distributed data centers, for capacity provisioning inside a data center and for right-sizing data center networks. We also investigate the impact of dynamic deferral on user satisfaction and devise techniques to capture the loss in value of deferred execution by utility functions and make a trade-off between user satisfaction and energy efficiency. In the context of smart grid, we have proposed EV task deferral techniques for peak shaving, valley filling and increase renewable energy usage.
Synergy Labs is lead by Yuvraj Agarwal and Bharathan Balaji, and is focused on energy efficiency in buildings. Research areas include designing systems that interface with the building infrastructure in order to reduce electrical consumption. Buildings present a prototypical cyber physical system, combining computation with the physical world. Our work has led us to implement a sensor network embedded in the physical fabric to drive building controls for optimal efficiency.
A series of projects that address energy-aware computing for computers and wireless communication in mobile devices. One project seeks to reduce energy consumption of PCs by allowing computers to maintain network traffic while in sleep mode. Another seeks to reduce energy comsumption in wireless devices by leveraging multiple heterogeneous wireless interfaces with different radio characteristics.
We have extensively metered the UCSD campus and the CSE building to determine where energy is actually being consumed. From the plug loads to the HVAC system, find out how much energy each end-use is actually consuming. Also we can compare buildings against each other and figure out how much energy the campus as a whole requires.