Previous Research Projects
Our previous research projects focused on system architecture, design technology, and fundamental theory and algorithms
as applied to embedded devices and computer systems.
Synergy Labs is headed by Yuvraj Agarwal, and is focused on energy efficiency in buildings. Research areas include designing systems that interface with the building infrastructure in order to reduce electrical consumption. Buildings present a prototypical cyber physical system, combining computation with the physical world. Our work has led us to implement a sensor network embedded in the physical fabric to drive building controls for optimal efficiency.
The Non-volatile Systems Laboratory (NVSL) was founded in 2008 and focuses on developing hardware and software prototypes to understand the hardware, software, security, and reliability implications of non-volatile, sol$
SPARK is a C-to-VHDL high-level synthesis framework that employs a set of innovative compiler, parallelizing compiler, and synthesis transformations to improve the quality of high-level synthesis results. The compiler transformations have been re-instrumented for synthesis by incorporating ideas of mutual exclusivity of operations, resource sharing and hardware cost models. The SPARK parallelizing high-level synthesis methodology is particularly targeted to multimedia and image processing applications along with control-intensive microprocessor functional blocks.
A series of projects that address energy-aware computing for computers and wireless communication in mobile devices. One project seeks to reduce energy consumption of PCs by allowing computers to maintain network traffic while in sleep mode. Another seeks to reduce energy comsumption in wireless devices by leveraging multiple heterogeneous wireless interfaces with different radio characteristics.
Collecting data from spatially distributed sensors is a generic form of sensor network applications. Multihop forwarding approach has been broadly used for this purpose, but it can be inefficient in terms of energy consumpt$ This data mule approach significantly reduces energy consumption at each node. However, a downside of this approach is an increased data delivery latency, and thus we should optimize the motion of data mule so that we can minimize the latency.
We have extensively metered the UCSD campus and the CSE building to determine where energy is actually being consumed. From the plug loads to the HVAC system, find out how much energy each end-use is actually consuming. Also we can compare buildings against each other and figure out how much energy the campus as a whole requires.
The goal of the Balboa project is to investigate the usage of high level methodologies, languages and CAD tools for system-on-chip architectural modeling. The research is divided into three sub-projects, which are: Structured system composition, Concurrency exploitation and simulation efficiency, and Design composition vizualisation and visual formalisms.
The goal of COPPER project is to build and demonstrate a capability in hardware (processor-memory) and software (compilers) for management of power resources and its tradeoff against speed, accuracy and throughput needs.
The RUNES project has a vision to enable the creation of large-scale, widely distributed, heterogeneous networked embedded systems that interoperate and adapt to their environments. The inherent complexity of such systems must be simplified for programmers if the full potential for networked embedded systems is to be realised. The widespread use of network embedded systems requires a standardised architecture which allows self-organisation to suit a changeable environment.
The FORGE project is a framework for optimization of distributed embedded systems software, with the goal of overcoming the above mentioned challenges. We integrate the middleware abstraction layer with the hardware/OS abstraction layer and study mechanisms for capturing resources/architectures at these two levels and allowing interactions between the levels.
CATS: Cycle Accurate Transaction-driven Simulation Framework (CATS)
The cycle accurate transaction-driven simulation (CATS) framework provides
simulation performance comparable to bus transaction accurate (BTA) transaction
level model (TLM) while maintaining accuracy comparable to bus cycle accurate
(BCA) TLM. Combined with other optimizations, the CATS aims to achieve the state
of art simulation performance for multi-processor system on a chip (MPSoC)