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Books

• "Formal Methods and Models for System Design, A System Level Perspective", edited by R. Gupta, P. Le Guernic, S. Shukla and J.P. Talpin, Kluwer Academic Publishers, June 2004
• "SPARK: A Parallelizing Approach to the High-Level Synthesis of Digital Circuits", Sumit Gupta, R.K. Gupta, N.D. Dutt and A. Nicolau, Kluwer Academic Publishers, May 2004

2008

• "SwitchR: Reducing System Power Consumption in a Multi-Client Multi-Radio Environment," Y. Agarwal, T. Pering, R. Want, R. Gupta, 12th IEEE International Symposium on Wearable Computers (ISWC), October 2008.
• "A Gateway Node with Duty-Cycled Radio and Processing Subsystems for Wireless Sensor Networks", Zhong Yi Jin, Curt Schurgers, R. Gupta, ACM Transactions on Design Automation in Electronic Systems, Accepted June 2008.
• "Validating High-Level Synthesis,"S. Kundu, S. Lerner, R. Gupta, International Conference on Computer Aided Verification (CAV'08), Princeton, NJ, USA, July 2008.
• "Improved Distributed Simulation of Sensor Networks based on Sensor Node Sleep Time", Z. Jin, R. Gupta, 4th IEEE/ACM International Conference on Distributed Computing in Sensor Systems (DCOSS), June 2008
• "Improving the Data Delivery Latency in Sensor Networks with Controlled Mobility", R. Sugihara, R. Gupta, 4th IEEE/ACM International Conference on Distributed Computing in Sensor Systems (DCOSS), June 2008 (to appear) (Best paper for Systems track)
  
• "Partial Order Reduction for Scalable Testing of SystemC TLM Designs", S. Kundu, M. Ganai, R. Gupta, Design Automation Conference (DAC'08), Anaheim, CA, USA, 2008.
  
• "Programming Models for Sensor Networks: A Survey", R. Sugihara, R. Gupta,  ACM Transactions on Sensor Networks, vol.4, issue 2, March 2008
• "Temperature Control of High-Performance Multi-Core Platforms Using Convex Optimization," S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. Boyd, L. Benini, G. De Micheli, Design Automation and Test in Europe (DATE), March 2008.
  

2007

• "Scheduling under Location and Time Constraints for Data Collection in Sensor Networks"
  Ryo Sugihara and Rajesh K. Gupta,
  in 28th IEEE Real-Time Systems Symposium (RTSS) (work-in-progress session),
  Tucson, Dec. 2007

• "A different approach to sensor networking for SHM: Remote powering and interrogation with unmanned aerial vehicles", Todd, M., Mascarenas, D., Flynn, E., Rosing, T., Lee, B., Musiani, D., Dasgupta, S., Kpotufe, S., Hsu, D., Gupta, R., Park, G., Overly, T., Nothnagel, M., Farrar, C., Proceedings of the 6th International workshop on Structural Health Monitoring, 2007.

• "Automated Refinement Checking of Concurrent Systems", S. Kundu, S. Lerner, R. Gupta, ICCAD, November 2007
  
• "Reactivity in SystemC Transaction-level Models," F. Doucet, R. K. Shyamsundar, I. Krueger, S. Joshi, R. Gupta, Haifa Verification Conference, October 2007
• "Temperature-Aware Processor Frequency Assignment for MPSOCs Using Convex Optimization," S. Murali, D. Atienza, G. De Micheli, R. Gupta, IEEE/ACM/IFIP CODES+ISSS part of ESWeek, September 2007
  
• “An Embedded Platform with Duty-Cycled Radio and Processing Subsystem for Wireless Sensor Networks”,  Z. Jin, C. Schurgers and R. Gupta, Embedded Computer Systems: Architectures, Modeling and Simulation Conference (SAMOS), July 2007
• "Wireless Wakeups Revisited: Energy Management for VoIP overWi-Fi Smartphones", Y. Agarwal, R. Chandra, A. Wolman, P. Bahl, K. Chin and R. Gupta, MobySys'07, Puerto Rico, June 2007
  
• "CATS: Cycle-Accurate Transaction-Driven Simulation with Multiple Processor Simulators", D Kim, R Gupta and S Ha, DATE 2007, April 2007, Nice France
• “Compositional Reactive Semantics of SystemC and Verification in RuleBase,” R.K. Shyamasundar, F. Doucet, R. Gupta, and I. H. Krüger, Proc. of the Workshop on Next Generation Design and Verification Methodologies for Distributed Embedded Control Systems. Jan. 2007.

2006

• "Optimized Slowdown in Real-Time Task Systems", R. Jejurikar, and R. Gupta, In IEEE Transactions on Computers, Vol.55, Iss.12, Dec. 2006, pp. 1588-1598
• "Phase Guided Sampling for Efficient Parallel Application Simulation", J. Namkung, D. Kim, R. Gupta, I. Kozintsev, J.-P. Bouget and C. Dulong,  CODES+ISSS’06, October 22–25, 2006, Seoul, Korea.
  
• "Declarative Resource Naming for Macroprogramming Wireless Networks of Embedded Systems", C. Intagonwiwat, R. Gupta and A. Vahdat, To appear in International Workshop on Algorithmic Aspects of Wireless Sensor Networks (ALGOSENSORS), Venice, Italy, July 15 2006.
• "Energy Aware Task Scheduling with Task Synchronization for Embedded Real-Time Systems", R. Jejurikar and R. Gupta,  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp 1024--1037, Vol. 25, no. 6, June 2006
• "Energy Efficient Watermarking on Mobile Devices using Proxy-based Partitioning", A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt, and R. Gupta, In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 14, no 6, pp 625- 636, June 2006
  
• "CoolSpots: Reducing Power Consumption Of Wireless Mobile Devices Using Multiple Radio Interfaces", T. Pering, Y. Agarwal, R. Gupta and R. Want, Fourth International Conference on Mobile Systems, Application and Services (MobiSys), Uppsala, Sweden, June 18-22, 2006
  
• “Parallel Co-simulation Using Virtual Synchronization with Redundant Host Execution”, D. Kim, S. Ha and R. Gupta, Proc. of  Design, Automation and Test in Europe Conference (DATE), Munich, Germany March 6-10 2006
  

2005

• "A Compositional Behavioral Modeling Framework for Embedded System Design and Conformance Checking", J.P.Talpin, P. Le Guernic, S.K. Shukla and R.Gupta, International Journal of Parallel Programming, Volume 33, Issue 6, Dec 2005, Pages 613 - 643
  
• "An Overview of the Competitive and Adversarial Approaches to Designing Dynamic Power Management Strategies", S. Irani, G. Singh, S.K. Shukla, and R.K. Gupta, Trans. on Very Large Scale Integration Systems, December 2005
• "Energy Analysis of Multimedia Watermarking on Mobile Handheld Devices", A. Kejariwal, S. Gupta, A. Nicolau, N. Dutt and R. Gupta, In Proc. of 3rd workshop on Embedded Systems for Real-Time Multimedia (ESTIMEDIA'05), Sept. 2005
• "Dynamic Phase Analysis for Cycle-Close Trace Generation", C. Pereira, J.Lau, B. Calder and R. Gupta, In Proc. of International Conference on Hardware/Software Codesign and System Synthesis (CODES/ISSS'05), Sept. 2005.
• "A Verification Approach for GALS Integration of Synchronous Components", F. Doucet, M. Menarini, I. H. Krueger and R. Gupta, In Proc of the Second International Workshop on Globally Asynchronous Locally Synchronous Design (FMGALS'05), July 2005.
  
• "Energy Aware Non-Preemptive Scheduling for Hard Real-Time Systems", R. Jejurikar and R. Gupta, In Proc. of 17^th Euromicro Conference on Real-Time Systems (ECRTS '05), July 2005.
• "Dynamic Slack Reclamation with Procrastination Scheduling in Real-Time Embedded Systems",  R. Jejurikar and R. Gupta, In Proc. of  42^nd Design Automation Conference (DAC '05), June 2005.
• "Trace-Driven HW/SW Cosimulation Using Virtual Synchronization Technique", D. Kim, Y.Yi and S. Ha, In Proc. of  42^nd Design Automation Conference (DAC '05), June 2005.
• "Line Size Adaptivity Analysis of Parameterized Loop Nests for Direct Mapped Data Cache", P.D'Alberto, A. Nicolau, A. Veidenbaum and R. Gupta, IEEE Transactions on Computers, Vol. 54, No. 2, pp 185-197, Febuary 2005.
• "Energy Aware Wireless Systems with Adaptive Power-Fidelity Tradeoffs", V. Raghunathan, C. Pereira, M. B. Srivastava and R. Gupta, IEEE Transactions on VLSI Systems, Volume 13, No. 2, Febuary 2005.
• "Using Probabilistic Model Checking for Dynamic Power Management", G. Norman, D. Parker, M. Kwiatkowska, S. Shukla and R. Gupta, Journal of Formal Aspects of Computing, 2005.
• "Dynamic Power Management using On Demand Paging for Networked Embedded Systems", Y. Agarwal, C. Schurgers adn R. Gupta, In Proc. of Asia-South Pacific Design Automation Conference (ASPDAC'05), Jan 2005.
• "Static Analysis and Automatic Code Synthesis of flexible FSM Model", D.Kim and S. Ha, In Proc. of Asia-South Pacific Design Automation Conference (ASPDAC'05), Jan 2005.

2004

• "Algorithms for Power Savings", S. Irani, S. Shukla and R.Gupta, Accepted for publication in Journal of Algorithms, 2004
  
• "Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis", S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau, ACM Transactions on Design Automation for Electronic Systems, Volume 9, Issue 4, pages 441-470, October 2004.
• "Integrating Preemption Threshold Scheduling and Dynamic Voltage Scaling for Energy Efficient Real-Time Systems", R. Jejurikar and R. Gupta , In Proc. of International Conference on Real-Time and Embedded Computing Systems and Applications (RTCSA '04), Aug 2004.
• "Dynamic Voltage Scaling for System-wide Energy minimization in Real-Time Embedded Systems", R. Jejurikar and R. Gupta, In Proc. of International Symposium on Low Power Electronics and Design (ISLPED '04), Aug 2004.
• "Formal Refinement-checking in a System-level Design Methodology", J.P. Talpin, P. Le Guernic, S. Shukla, F. Doucet and R. Gupta, Fundamenta Informaticae,
  Volume 62, Number 2, pages 243-273, July 2004.
• "Optimized Slowdown in Real-Time Task Systems", R. Jejurikar and R. Gupta, In Proc. of Euromicro Conference on Real-Time Systems (ECRTS '04), Jun-Jul, 2004.
• Procrastination Scheduling for Fixed Priority Real-Time Systems", R. Jejurikar and R. Gupta, In Proc. of  ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES '04), June, 2004
• Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems", R. Jejurikar, C. Pereira and R. Gupta, In Proc. of Design Automation Conference (DAC '04), June 2004.
• "A Behavioral Type Inference System for Compositional System-on-Chip Design", J.-P. Talpin, D. Berner, S. Shukla, A. Gamatie, P. Le Guernic and R. Gupta, In Application of Concurrency to System Design (ACSD), Hamilton, Ontario, Canada, June 2004.
• "System-wide Energy Minimization in Real-Time Embedded Systems", R. Jejurikar, R. Gupta, CECS Technical Report 04-14, May 2004.
• "Optimized Slowdown in Real-Time Task Systems", R. Jejurikar, R. Gupta, CECS Technical Report 04-10, April 2004.
• "Procrastination Scheduling in Fixed Priority Real-Time Systems", R. Jejurikar, R. Gupta, CECS Technical Report 04-09, April 2004.
• "Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis", S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta and A. Nicolau, IEEE Transactions on Computer-Aided Design, Feb. 2004.
• "Integrating Processor Slowdown and Preemption Threshold Scheduling for Energy Efficiency in Real-Time Embedded Systems", R. Jejurikar, R. Gupta, CECS Technical Report 04-03, Feb 2004
• "Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow", S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau, In Proc of Design, Automation and Test in Europe (DATE), Paris, France, Feb. 2004.
• "Energy Aware Non-preemptive Scheduling for Hard Real-Time Systems", R. Jejurikar and R. Gupta, CECS Technical Report 04-01, Jan., 2004.
• Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures, Nikhil Bansal, Sumit Gupta, Nikil Dutt, Alexandru Nicolau, Rajesh Gupta, DATE 2004: 474-479
• Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures, Nikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta,  FPL 2004: 891-899

2003

• "Balboa: A Component-Based Design Environment for System Models", F. Doucet, S. Shukla, M. Otsuka and R. Gupta, In IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, Vol 22(12), Dec. 2003.
• "Petri Net-based Thread Composition for Improved System Level Simulation", N. Savoiu, S. Shukla and R. Gupta, CECS Technical Report 03-39, Dec. 2003.
• "Formal Methods for Dynamic Power Management", R. Gupta, S. Irani and S. Shukla, In Proc. of International Conference on Computer Aided Design, Nov. 2003
  
• "Hardware and Interface Synthesis of FPGA Blocks using Parallelizing Code Transformations", S. Gupta, M. Luthra, N.D. Dutt, R.K. Gupta and A. Nicolau, Invited talk at the special session on Synthesis For Programmable Systems at the International Conference on Parallel and Distributed Computing and Systems, Nov. 2003.
• "Dynamically Increasing the Scope of Code Motions during the High-Level Synthesis of Digital Circuits", S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau, Invited Paper in Special Issue of IEE Proceedings: Computers and Digital Technique: Best of DATE 2003, Vol 150(5), Sep. 2003.
• "Dual Mode Algorithm for Energy Aware Fixed Priority Scheduling with Task Synchronization", R. Jerjurikar and R. Gupta, In Proc. of Workshop on Compilers and Operating Systems for Low Power (COLP), Sep. 2003.
• "Online Strategies for Dynamic Power Management in Systems with Multiple Power-Saving States", S. Irani, S. Shukla and R. Gupta, In ACM Transactions on Embedded Computing Systems, August 2003
• "Polychrony for Formal Refinement-checking in a System-level Design Methodology", J.-P. Talpin, P. Le Guernic, S. K. Shukla, R. Gupta and F. Doucet, In Proc of Application of Concurrency to System Design (ACSD), Guimarães, Portugal, June 2003.
• "On Demand Paging Using Bluetooth Radios on 802.11 Based Networks", Y. Agarwal and R. Gupta, CECS Technical Report 03-22, June, 2003.
• "Energy Efficient Communication for Reliability and Quality Aware Sensor Networks", C. Pereira, S. Gupta, K. Niyogi, I. Lazaridis, S. Mehrotra and R. Gupta, Technical Report 03-15, CECS UC Irvine, Apr. 2003.
• "Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow", S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau, Technical Report 3-14, CECS, UC Irvine, Apr. 2003.
• "Introspection in System-Level Language Frameworks: Meta-level vs. Integrated", F. Doucet, S. Shukla and R. Gupta, In Proc. of Design Automation and Test in Europe (DATE), Munich, Germany, March 2003.
• "Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs", S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau, In Proc. of Design, Automation and Test in Europe (DATE), Munich Gernany, March 2003.
• "A Polychronous Model for High-level Component-based System Design", J.-P. Talpin, P. Le Guernic, S. K. Shukla, R. Gupta and F. Doucet, In Proc. of Digital Automation and Test Europe (DATE), Munich, Germany, Mar. 2003.
• "Dual Mode Frequency Inheritance Algorithm", R. Jejurikar, C. Pereira and R. Gupta, Technical Report 03-07, CECS, UC Irvine, Feb. 2003.
• "Typing Abstractions and Management in a Component Framework", F. Doucet, S. Shukla and R. Gupta, In Proc. of Asia and South Pacific Design Automation Conference (ASPDAC), Kitakyushi, Japan, Jan. 2003.
• "SPARK : A High-Level Synthesis Framework For Applying Parallelizing Compiler Transformations", S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau, International Conference on VLSI Design (Best Paper Award), Jan. 2003.
• "Algorithms for Power Savings", S. Irani, S. Shukla and R. Gupta, ACM-SIAM symposium on Discrete Algorithms, Jan 2003

2002

• "Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis", S. Gupta, N.D. Dutt, R.K. Gupta and A. Nicolau, Technical Report 2-35, CECS, UC Irvine, Dec. 2002.
• "Computing static slowdown factors under EDF scheduling when deadline less than period", R. Jejurikar and R. Gupta, Technical Report 02-36, CECS, UC Irvine, Dec. 2002.
• "Structured Composition Techniques for Embedded Systems", R. Gupta, S. Shukla and F. Doucet. In Proc. of International Conference on High Performance Computing (HiPC'02), Dec. 2002.
• "Formal Analysis and Validation of Continuous-Time Markov Chain based System Level Power Management Strategies", G. Norman, D. Parker, M. Kwiatkowska, S. Shukla and R. Gupta, In Proc. of IEEE International High Level Design Validation and Test Workshop (HLDVT'02), 2002
  
• "Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis", S. Gupta, M. Reshadi, N. Savoiu, N.D. Dutt, R.K. Gupta and A. Nicolau, International Symposium on System Synthesis (ISSS), Oct. 2002.
• "Using Global Code Motions to Improve the Quality of Results for High-Level Synthesis", S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta and A. Nicolau, Technical Report 2-29, CECS, UC Irvine, Oct. 2002.
• "Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems", R. Jerjurikar and R. Gupta, In Proc of International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), Oct. 2002.
• "Energy Aware EDF Scheduling with Task Synchronization for Embedded Real-Time Operating Systems", R. Jerjurikar and R. Gupta, In Proc. of Workshop on Compilers and Operating Systems for Low Power (COLP), Sep. 2002.
• "Energy Aware EDF Scheduling with Task Synchronization for Embedded Real Time Systems", R. Jejurikar and R. Gupta, Technical Report 02-24, CECS, UC Irvine, Aug. 2002.
• "PASA: A Software architecture for building power aware embedded systems", C. Pereira, R. Gupta, M. Srivastava, In Proc. of the IEEE CAS Workshop on Wireless Communications and Networking - Power efficient wireless ad hoc networks, June 2002.
• "Energy Aware Task Scheduling with Task Synchronization for Embedded Real Time Systems", R. Jejurikar and R. Gupta, Technical Report 02-21, CECS UC Irvine, June 2002.
• "Coordinated Transformations for High-Level Synthesis of High Performance Microprocessor Blocks",
  S. Gupta, T. Kam, M. Kishinevsky, S. Rotem, N. Savoiu, N.D. Dutt, R.K. Gupta and A. Nicolau,
  In Proc. of the Design Automation Conference (DAC), June 2002.
• "An Environment for Dynamic Component Composition for Efficient Co-Design", F. Doucet, M. Otsuka, S. Shukla, and R. Gupta, In Proc. Design Automation and Test in Europe (DATE), Paris, France, March 2002.
• "A Software Architecture for Building Power Aware Real Time Operating Systems" C. Pereira, V. Raghunathan, S. Gupta, R. Gupta and M. Srivastava, Technical Report 02-07, CECS UC Irvine, March 2002.
• "Efficiency and Optimality of Static Slowdown for Periodic Tasks in Real-Time Embedded Systems", R. Jejurikar and R. Gupta, Technical Report 02-03, CECS UC Irvine, Mar. 2002.
• "Power-Aware Computing: Chapter 8 - Power-Aware API for Embedded and Portable Systems", C. Pereira, R. Gupta, P. Spanos, M. Srivastava, Kluwer Academic Publishers.
• "Computing Optimal Static Slowdown Factors for Periodic Tasks under EDF Scheduling", R. Jejurikar and R. Gupta, Technical Report 02-02, ICS UC Irvine, Jan. 2002.

2001

• "A Model Checking Approach to Evaluating System Level Dynamic Power Management Policies for Embedded Systems", S. Shukla and R. Gupta, In Proc. of IEEE International High Level Design
  Validation and Test Workshop (HLDVT'01), 2001
  
• "Interoperability as a Design Issue in C++ Based Modeling Environment", F. Doucet, R. Gupta, M. Otsuka, P. Schaumont and S. Shukla, In Proc. of the International Symposium on System Synthesis (ISSS), Oct. 2001.
• "Conditional Speculation and its Effects on Performance and Area for High-Level Synthesis", S. Gupta, N. Savoiu, N.D. Dutt, R.K. Gupta and A. Nicolau, International Symposium on System Synthesis (ISSS), Oct. 2001.
• "Efficient System Level Co-Design Environment using Split Level Programming", F. Doucet, M. Otsuka, R. Gupta and S. Shukla, Technical Report 01-34, CECS, UC Irvine, July 2001.
• "Conditional Speculation and its Effects on Performance and Area for High-level Synthesis", S. Gupta, N. Savoiu, N. Dutt, R Gupta and A. Nicolau, Technical Report 1-25 ICS, UC Irvine June 2001.
• "Speculation Techniques for High Level synthesis of Control Intensive Designs", S. Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta, A. Nicolau, In Proc. of Design Automation Conference (DAC), June 2001.
• "Structural Design Composition for C++ Hardware Models", F. Doucet, V. Sinha and R. Gupta, In Proc. Computer Society VLSI Workshop, 2001.
• "Efficient Usage of Concurrency Models in an Object-Oriented Co-design Framework", P. Garg, S. Shukla and R. K. Gupta, In Proc. Design Automation and Test in Europe (DATE), March 2001.

2000

• "Speculation Techniques for High Level synthesis of Control Intensive Designs", S. Gupta, N. Savoiu, S. Kim, N.D. Dutt, R.K. Gupta and A. Nicolau, Technical Report 00-40, ICS, UC Irvine, Dec. 2000.
• "Analysis of High-level Address Code Transformations for Programmable Processors",S. Gupta, R. K. Gupta, M. Miranda, F. Catthoor, In Proc. Design, Automation and Test in Europe (DATE), Paris, March 2000.
• "YAML: A Tool for Design Visualization and Capture", V. Sinha, F. Doucet, C. Siska, R. K. Gupta, S. Liao and A. Ghosh, In Proc. International Symposium on System Synthesis (ISSS), 2000.
• "Microelectronic System-on-Chip Modeling using Objects and their Relationships", F. Doucet, V. Sinha and R. K. Gupta, OSEE 2000.
• "Analysis of High-level Address Code Transformations for Programmable Processors", S. Gupta, M. Miranda, F. Catthoor, R. K. Gupta, Technical Report 00-04, ICS, UC Irvine, Apr. 2000.
• "Design Visualization and Entry using Structural and Functional Entities", V. Sinha and R. K. Gupta,
  Technical Report 00-05, CECS, UC Irvine, Feb. 2000.
• "Debugging of Polymorphic SystemC/C++ Code for Hardware Design", F. Doucet and R. K. Gupta, Technical Report 00-06, CECS, UC Irvine, Feb. 2000.