Previous Research Projects
Our previous research projects focused on system architecture, design technology, and fundamental theory and algorithms
as applied to embedded devices and computer systems.
Current Projects
Past Projects
The Balboa Project
The goal of the Balboa project is to investigate the usage of high level methodologies, languages and CAD tools for system-on-chip architectural modeling. The research is divided into three sub-projects, which are: Structured system composition, Concurrency exploitation and simulation efficiency, and Design composition vizualisation and visual formalisms.
COPPER: Compiler-Controlled Continuous Power-Performance Management
The goal of COPPER project is to build and demonstrate a capability in hardware (processor-memory) and software (compilers) for management of power resources and its tradeoff against speed, accuracy and throughput needs.
RUNES: Reconfigurable Ubiquitous Networked Embedded Systems
The RUNES project has a vision to enable the creation of large-scale, widely distributed, heterogeneous networked embedded systems that interoperate and adapt to their environments. The inherent complexity of such systems must be simplified for programmers if the full potential for networked embedded systems is to be realised. The widespread use of network embedded systems requires a standardised architecture which allows self-organisation to suit a changeable environment.
FORGE: A Framework for Optimization of Distributed Embedded Systems Software
The FORGE project is a framework for optimization of distributed embedded systems software, with the goal of overcoming the above mentioned challenges. We integrate the middleware abstraction layer with the hardware/OS abstraction layer and study mechanisms for capturing resources/architectures at these two levels and allowing interactions between the levels.
CATS: Cycle Accurate Transaction-driven Simulation Framework (CATS)
The cycle accurate transaction-driven simulation (CATS) framework provides
simulation performance comparable to bus transaction accurate (BTA) transaction
level model (TLM) while maintaining accuracy comparable to bus cycle accurate
(BCA) TLM. Combined with other optimizations, the CATS aims to achieve the state
of art simulation performance for multi-processor system on a chip (MPSoC)
system. See '4. performance results part' of
the CATS document.