Joel D. Coburn
Status
I completed my PhD in the department of computer science and engineering at University of California, San Diego.I will be joining Google in the fall.
Contact
Dept. of Computer Science & EngineeringOffice: CSE building, room 2150
Address: 9500 Gilman Drive #0404, La Jolla, CA 92093-0404
Phone: 858-534-9895
Email: jdcoburn at cs dot ucsd dot edu
Research
I worked in the Non-Volatile Systems Lab under the guidance of professors Steve Swanson and Rajesh Gupta. My research area is computer systems architecture, and my interests include new system architectures for exploiting emerging technologies, designing scalable and efficient storage systems, and hardware/software support for parallel and heterogeneous architectures. My most recent work focused on how to integrate new, non-volatile memory technologies such as phase-change memory into computer systems to provide fast and safe access to storage.- Providing Safe, User Space Access to Fast, Solid State Disks, A.M. Caulfield, T.I. Mollov, L. Eisner, A. De, J. Coburn, S. Swanson, to appear at the Conference on Architectural Support for Programming Languages and Operating Systems
(ASPLOS), March 2012.
- Computational Mass Spectrometry in a Reconfigurable Coherent Coprocessing Architecture, D.S. Yalamarthy, J. Coburn, R.K. Gupta, G. Edwards, M. Kelly, IEEE Design and Test of Computers, 28:58-67, 2011.
- NV-Heaps: Making Persistent Objects Fast and Safe with Next-Generation, Non-Volatile Memories, J. Coburn, A.M. Caulfield, A. Akel, L.M. Grupp, R.K. Gupta, R. Jhala, S. Swanson, Conference on Architectural Support for Programming Languages and Operating Systems
(ASPLOS), March 2011.
- Moneta: A High-performance Storage Array Architecture for Next-generation, Non-volatile Memories, A.M. Caulfield, A. De, J. Coburn, T.I. Mollov, R.K. Gupta, S. Swanson, International Symposium on Microarchitecture (MICRO), December 2010.
- Understanding the Impact of Emerging Non-Volatile Memories on High-Performance, IO-Intensive Computing, A.M. Caulfield, J. Coburn, T.I. Mollov, A. De, A. Akel, J. He, A. Jagatheesan, R.K. Gupta, A. Snavely, S. Swanson, International Conference for High Performance Computing, Networking, Storage and Analysis (SC), November 2010.
- Characterizing Flash Memory: Anomalies, Observations, and Applications, L.M. Grupp, A.M. Caulfield, J. Coburn, E. Yaakobi, S. Swanson, P. Siegel, and J. Wolf, International Symposium on Microarchitecture (MICRO), December 2009.
- Streamware: Programming
General-Purpose Multicore Processors Using Streams, J. Gummaraju,
J. Coburn, Y. Turner, M. Rosenblum, Conference on
Architectural Support for Programming Languages and Operating Systems
(ASPLOS), March 2008.
- Architectural Support
for the Stream Execution Model on General-Purpose Processors,
J. Gummaraju, M. Erez, J. Coburn, M. Rosenblum,
W. Dally, Conference on Parallel Architectures and Compilation
Techniques(PACT), September 2007.
- Security-Enhanced Communication
Architecture, J. Coburn, S. Ravi, A. Raghunathan,
S. Chakradhar, Conference on Compilers, Architectures, and
Synthesis for Embedded Systems (CASES), September 2005.
- Power Emulation: A New
Paradigm for Power Estimation, J. Coburn, S. Ravi,
A. Raghunathan, Design Automation Conference (DAC), June
2005.
- Hardware Accelerated
Power Estimation, J. Coburn, S. Ravi, A. Raghunathan, Design,
Automation, and Test in Europe (DATE), March 2005.
Teaching
In yet another past life, I was a grad student at Stanford. I had the opportunity to TA the following courses.- EE108A: Digital Systems
I, the course formerly known
as EE121: Digital Design
Lab
- EE183: Advanced Logic
Design Laboratory now replaced
by EE109: Digital Design
Lab
- EE282: Computer
Systems Architecture
Last modified August 9, 2012
by Joel D. Coburn.