This on-line material is being provided in the interest of rapid dissemination of information related to the research work conducted by the MESL group. Some or all of the material here may be covered by copyright owned by the respective authors. You may browse the material at your convenience as you would in a public library. Permission is also granted to make a hard copy for personal use without fee provided that the copied material clearly indicates the author and source of the material and any original copyright notations are unaltered on every portion of the referenced material. Retrieval, copy, or distribution of any material herein for profit or any commerical advantage may violate the copyright protection law and requires prior written permission of the copyright owners.
Keynote, ARM 2006,
ECSI/UBS Forum at
FDL2, Darmstadt, September 2006
Slides
ECSI/UBS Forum at FDL2,
Slides
Keynote Talk,
Automotive
Software Workshop (ASWD'06),
Slides
Dinner Talk, The
Center for Integrated Systems,
Slides
Keynote, ESL
Workshop, January
2006
ESL is often seen as a proxy for the movement of design methods and
tools to a
higher level, much as RTL was for a generation before it. Beyond the
semantics,
in practical terms it refers to a collection of technologies for
improved
system-level design exploration. This exploration is critical to the
coming
generations of microelectronic systems, often highly integrated for
cost,
performance, power reasons. Too many of these systems, from cellular
handsets
to consumer electronics applications, are designed as singular pieces
driven by
the availability of constituent components and component technologies
from
processors, radios to operating systems. To be successful, the design
houses
have to go beyond such constructions to defining platforms, their
system-level capabilities
and evolution. My thesis for this talk is that a successful adoption of
ESL is
crucial towards achieving the necessary competence and ownership of the
platform for their products. This is because the so-called ESL
technologies --
from component compositions, cosimulations
to
partitioning and verification -- provide the necessary insight to the
system
architect to be able to build out platform abstractions. Using
examples
from mobile computing platforms, I will illustrate the major points.
Slides
Co-design and Verification Seminar, Intel,
High level modeling of components and the ability to compose these into
system-level models are key to advancing
system design
methods. Recently, high level language models, such as C and C++, have
been
used to build component models, at least for chip design purposes.
These models
deploy a number of smarts and assists -- for modeling concurrency,
reactivity,
exceptions, synchronous/asynchronous behaviors, data types etc -- to
enable the
system designer build fairly detailed and (at least, cycle accurate)
models of
component behaviors. What happens when these models are composed --
often structurally
as a chip or system designer would -- into complete system models? Are
these
compositions even possible, and what semantic guarantees do the
composed models
carry? In this talk, I will examine the difficulties associated with buiilding a system design methodology based on
composition
of predesigned components, challenges and
our ongoing
work in this area. I would outline our approach to ensure correct
composition
of components, specifically in the concrete context of SystemC
models.
Slides
CANDE Panel, September 2005
Slides
Intel DTTC,
Slides
Construction and
Analysis of
Safe, Secure and Interoperable Smart Devices (CASSIS), Keynote, Nice,
March
2005
Changing location and changing operating conditions in networked mobile
devices
present many challenges to the application developer. Resource/energy
availability is no longer guaranteed and data availability is a
function of the
location where the computation is done and the geographical movement of
data to
support this computation. In this talk, we describe a reactive
framework that
provides a systematic treatment of mobility in application functions,
and uses
the features of environmental context as observables between
components.
Observable context features include communications, termination,
clocks,
location and energy availability. This provides a powerful formalism to
abstract important features of a mobile computing environment and help
design
services to support capabilities for location and energy awareness. We
will
discuss how location and energy awareness can be used for improved
device
design and its infrastructure.
Slides
Slides
Slides
Ziff-Davis, December 2003
Slides
Globecom,
San Francisco,
December 2, 2003
Slides
Micro 36,
Slides
ICCAD, November 11, 2003
Slides
Qualcomm, Nov, 2002
Abstract
Effective management of energy and power in microsystems
requires active participation of all the actors from applications to
system
software to network interfaces in making the right
power/performance/quality
choices. In this talk, I will describe results from our
ongoing work on characterization of effectiveness of the power
management
algorithms and a software architecture that enables the
application developer to turn the right hardware and subsystem
"knobs" based on application context and dynamically changing
performance/quality requirements.
Ongoing projects. Slides.
Presentation at HiPC02, December 2002.
Presentation at JPL-CASS Workshop, September 2002
Presentation at DATE 2002, March 2002
Presentation
at DATE
2002, March 2002
Presentation
at DATE
2002, March 2002
Presentation to Cal-IT2 Advisory Board, 2/8/02
Continuing trends in microelectronic technology are beginning to fundamentally alter the ground rules in the design of high performance circuit blocks and the role of interconnect between the circuit blocks. Our research group is particularly interested in understanding the impact of these technology trends for on-chip system architecture and design tools for the coming generations of process technologies.
This talk presents the case for adaptivity in system architectures -- from single-chip embeddable processor cores to multiprocessor systems -- that relies on application-driven hardware customization to achieve cost-effective system implementations. Architectural customization, achieved using synthesizable logic blocks and computer-aided design tools, is used to improve system performance while keeping system development and product costs down. We describe highlights from the on-going research activity on the Adaptive Memory Reconfiguration Management (AMRM) project that uses architectural adaptation to improve the performance of memory subsystem and communication resources.
This talk describes on-going research activity. We welcome participation and feedback from the audience. Further details and related publication pointers can be found at http://www.ics.uci.edu/~amrm.
We present an assessment of the technology trends and its implications for the computer systems architecture and design tools for the coming generations of process technologies. Based on technology projections from the SIA road-map, the cumulative effect of continuing increases in interconnect delay relative to gate switching would fundamentally alter the ground rules in the design of high performance circuit blocks and the role of interconnect between the circuit blocks. For instance, multiple storage elements could be located in a cycle period whereas block-level interconnect would no longer be a part of the cycle time. Architecturally, increased local decision making can be used to adapt a data-path to application-specific computational requirements. To illustrate how this adaptability can be used in efficient system architectures, we present highlights from the study of latency-hiding mechanisms to improve the interaction of processing and memory elements as a part of the on-going DARPA-sponsored project on high-performance data-intensive embedded computing.
From a design technology standpoint, language-level modeling and system co-design of hardware/software blocks under strict timing constraints present a special challenge to the next generation of system design tools. The new design technology must balance increasing technology dependence while advancing the level of abstraction towards target applications. I will present an overview of our work system-level CAD algorithms and describe how system design problems are addressed in a framework that allows the system architect to interactively explore intelligent design options without leaving the application development environment. This talk describes on-going research activity. We welcome participation and feedback from the audience.
Recent availability of cores, or pre-designed specialized function cells such as microprocessors, RF components, network interfaces, encryption and compression engines, has lead to exciting possibilities in building complex systems on a single-chip for embedded systems in a short time. Computing elements in these systems can be used to deliver application functionality, build and manage mobility, improve system performance, improve testability and reliability of these systems by adapting to application needs. A good system design, especially for single-chip implementations, requires effective integration of system digital and mixed-signal hardware, and software components. To handle system complexity, novel architectural approaches and system integration tools are needed to ensure that the system integration is correct, robust and manufacturing viable against the technology challenges and process variations and poor device characteristics particularly for analog and RF applications. In this talk, we will identify the bottlenecks in system co-design from specification to system partitioning and co-simulation challenges.
This talk presents an overview of the on-going research on design
tools for
single-chip embedded computing systems for moderately complex computing
and
non-computing applications such as network interfaces and broadband
switching
at
International Conference on Computer Aided Design, November, 1997.
A rate constraint on an operation specifies an upper or lower bound the rate of execution of the operation. In many performance critical embedded systems, rate constraints specify the throughput and response requirements on systems that are in continuous interaction with their environment. In case of a constraint violation, constraint "debugging" is needed to localize the source of constraint violation. The high complexity of these problems entails a systematic and automated framework to help the designer in producing correct system implementations in a short design time. In this talk, I will describe such a framework and its use in an interactive design environment. Constraint analysis is driven by a two-phase rate analysis algorithm that builds upon detection of maximum mean cycles in process graphs. I will describe a novel algorithm for solving maximum (and minimum) mean cycle problems that uses implicit process "unfolding" to improve upon the fastest known maximum mean cycle algorithms. Both asymptotic analysis and experimental results confirm the effectiveness of the new algorithm. We demonstrate by examples how the proposed rate analysis can be used in system design.
This on-line material is being provided in the interest of rapid dissemination of information related to the research work conducted by the MESL group. Some or all of the material here may be covered by copyright owned by the respective authors. You may browse the material at your convenience as you would in a public library. Permission is also granted to make a hard copy for personal use without fee provided that the copied material clearly indicates the author and source of the material and any original copyright notations are unaltered on every portion of the referenced material. Retrieval, copy, or distribution of any material herein for profit or any commerical advantage may violate the copyright protection law and requires prior written permission of the copyright owners.