CSE 237C: System Level Design Automation: Modeling, Synthesis and Validation

Professor Rajesh K. Gupta, EBU3B 2120, 858 822-4391, rgupta@ucsd.edu, Office Hours: Tuesday 2-4

Course Code: 627741 / Class meets MW 5:00-6:20PM Center Hall 206

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HOMEWORK 1. Pointer to HyVisual.

HOMEWORK 2 is available.

HOMEWORK 3 is available.

Pointer to Olympus

HOMEWORK 4

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Course Overview:

CSE 237C was earlier offered as Validation and Testing of Embedded Systems. The revised syllabus expands the scope to make it more design automation centric. The focus of the course is on models and algorithms behind optimization, synthesis and validation tools.

The focus of this course is on algorithms and methods behind optimization and synthesis tools in embedded systems.

Lecture Outline:

• Welcome and Introduction
1. HLS Retrospective
2. Core-based design
• Models of Computation: Introduction

1. Jantsch, Models of Embedded Computation
2. Gomes, Barros, Costa, Modeling Formalisms for Embedded System Design
• Models of Computation: Tagged Models, Theory (4 lectures)

1. Models of Computation
2. Graph Models
3. Data Flow Models
4. Hybrid Models: Ptolemy, CheckMate, Charon
• Architectural/Behavioral Synthesis (5 lectures)
1. Hardware Modeling and Behavioral Optimizations
2. Architectural Synthesis: Scheduling
3. Architectural Synthesis: Resource Allocation and Binding
4. Architectural Synthesis: Control Optimizations
5. Logic Synthesis and Optimizations
• Methods for power/performance optimization
1. Pointer to VLSI design tutorial
• Simulation: basics and acceleration
1. Yorktown Simulation Engine
2. Time Warp Operating System
• Parallel Discrete Event Simulation
1. Fujimoto
• Emulation (1 lecture)
• Verification and verification languages (2 lectures)

The laboratory component consists of experiments with CAD tools as well as programming exercises using tools such as Ptolemy.

Recommended Reading:

There is no textbook for the course. Material will be drawn from a variety of sources. Lectures notes and selection of readings distributed in the class are your primary source of reference material. In addition, class material is drawn from the following books (listed in no particular order):

• Modeling Embedded Systems and SOCs: Concurrency and Time in MOCs, Axel Jantsch, MKP 2005
• Synthesis and Optimization of Digital Circuits, Giovanni De Micheli, McGrawHill
• Theory of Modeling and Simulation, Zeigler, Praehofer, Kim, AP 2000
• Field Programmable Gate Arrays, Oldfield, Dorf, Wiley 1995
• Scott Hauck: The Roles of FPGAs in Reprogrammable Systems
• Hauck and Agarwal: Softare Technologies for Reconfigurable Systems
• Splash 2: FPGAs in a Custom Computing Machine, Buell, Arnold, Kleinfelder, IEEE 1996
• Gosling, Simulation in the design of digital electronic systems, Cambridge1993

Prerequisites:

Beyond an undergraduate degree in CS or EE, we assume familiarity with basics of algorithms, data structures, calculus, discrete math, digital design and computer architecture.

Course Logistics:

Three home works followed by a topic research and team project. Final grade will be based on performance in homeworks, final examination, topic research, project presentation and report. Final examination will be on June 13, 2008 7-10 PM.

Topic Research Suggestions:

You should look for a topic within the scope of the course that is narrow enough for you to explore, and read the important literature within a period of a week to ten days. Here are a few suggestions:

* Use of formal methods in non-functional verification (e.g., power, reliability)

* Application of model checking in hybrid systems
* Model checking in embedded software (asynchronous systems)
* Relationship of model checking to satisfiability or use of SAT solvers for automated model checking
* Acceleration of SAT solvers using custom hardware (FPGAs)
* State of Silicon IP cores, availability and standards
* Hybrid Modeling (or Verification) of Continuous and Discrete Time Systems
* Hybrid Modeling of Mixed Signal (analog and digital) Circuits and Systems
* Finite State Machines and Their Extensions
* Data Flow Graph Models and Their Extensions
* Current Practice in Software (Device Driver) Synthesis
* Verification of Device Drivers or Methods for Automated Verification of Device Drivers
* Architecture of Device Drivers in Windows Vista
* Programming Language Support for Verification (or Test)
* Loop-level Optimizations for Improved Synthesis
* Concurrency Enhancement Techniques for Hardware Synthesis
* High level Synthesis optimizations for low power
* HDL modeling and transformations for low power
* Code transformations / Loop transformations / Control optimizations for low power
* Testability and Coverage in HDL descriptions
* Models used in GALS (global asynchronous locally synchronous) systems
* Verification of GALS systems
* Causality in synchronous reactive models
* Ensuring causal behavior in discrete event models
* Algebraic modeling of discrete event systems
* Control-data-flow-graph models using in synthesis
* Need and use of two-level timing models (delta cycles) in discrete event systems
* Modeling of time and its precision in discrete event models
* Transactional models for communications

We will discuss these in the class on 8/9/2008. Those of you who have not sent in your selection, you are welcome to do this after our discussion on Wednesday.