The CATS Framework for MPSoC System

Key Features

• Cycle accurate transaction-driven simulation : BTA TLM has been used to enhance simulation performance but it has sacrificed accuracy . BCA TLM provides accuracy but is too slow. We propose cycle accurate transaction-driven simulation, shortly called CATS, to acquire advantages for both TLMs: performance and accuracy. To achieve the goal, CATS predicts events between processors and communication architecture by exploiting properties from communication protocol.
  
• Operating system emulation : It provides an emulation for operating system and supports application program interfaces (APIs) based on the emulation. APIs include task managements, synchronizations between tasks and data acquisitions. We provide several applications in Splash-2 benchmark as test benches. The emulation is only available for ARM processor.
• Skipping idle cycles by utilizing task behavior : Because we model behavior of operating system with the emulation, we can watch status of a processor in detail. Thus when a processor runs an idle task, we suspends the execution of the processor and resumes it when any interrupt from other processors arrives. However, during the suspension, the processor still cooperates with other processors to process cache coherence protocol.
• Configurable architecture description : Using the CATS framework, we can configure different processor models from SimpleScalar (ARM, Alpha, PowerPC, PISA) and communication architectures (ARM AHB, experimental NoC). It provides the same interfaces as SimpleScalar for processor configuration and defines our own for communication architectures.

Lists of On-Going Work

• We are trying to renovate communication architectures to support more complete sets of configurations and increase accuracy. We believe that the current implementation proves the concept for CATS but have not considered various effects from communication architectures. We hope that this renovation will make the framework more complete and flexible.
• We are trying to extend operating system emulation. Instead of hiding simulated cycles from OS in the framework, we will annotate simulated cycles to emulate different OSs and configurations of OS. It will help to explore OS design spaces for MPSoC. Moreover, we plan to support more devices and model their behaviors accurately.
  
• Although we integrated processor power model from sim-panalyzer experimentally, we are to devise a general framework to calculate powers in system level. Moreover, we also need to provide DVS and DPM mechanism in system level.
• We will provide switches between functional simulation and detailed simulation by system calls or a scheduler.
  
• We will apply OS emulation to Alpha, PowerPC and PISA.
  
• If you have our own ideas, you can join the improvement of the CATS framework.
  

Known Problems

• ARM cross compiler have some bugs in double operations. Because of those bugs, we can not make several applications in Splash-2 benchmark work.
• We strongly recommend to use malloc function calls before you create new tasks. The calls sometimes corrupt behavior of the framework. We are looking into the bug.
• API for task managements and synchronizations have some bugs. Most of experiments are OK but sometimes they bring problems. If it happens, you can see the error message. We are also looking into this bug.
  
• There are some timing issues when we implement communication architecture. Those issues brings inaccurate timings. Moreover, the  implementation for cache coherence protocol is not flexible and inefficient. We are revising the framework.

Downloads

• This documents explains the CAT framework including installation, usages and performance values
  
• To get the framework, please request me through e-mail..
  

Acknowledgements

• The CATS framework is being developed with supports from a gift from Intel Corporation, a grant from UC Discovery program and a post doctoral research program from Ministry of Information and Communication (MIC, ROK).
  
• We thank people who developed different processor models for SimpleScalar, a power model for ARM and Splash-2 benchmark.
• Processor models of SimpleScalar follow license terms for their owns.